1. Field of the Invention
The present invention relates to a solid-state image pickup apparatus, and in particular to a solid-state image pickup apparatus that is capable of adding signals from pixels.
2. Description of the Related Art
In recent years, solid-state image pickup apparatuses have been used in increasingly wide application areas and are also used in, for example, digital still cameras (hereinafter called DSCs). There has been active competition in DSCs from the view point of increasing resolution by increasing the number of pixels. There exist products with a resolution higher than ten million pixels. In addition to higher resolution, a movie function is also required. For instance, there exist products capable of outputting VGA size data (640×480 pixels) at a rate of 30 frames per second (30 fps). Demand for higher output rates is expected.
In an operation mode which requires a high output rate, an operation called pixel addition is known. Pixel addition allows the number of signals output from a solid-state image pickup apparatus to be decreased by adding signals from a plurality of pixels, while suppressing degradation of image quality.
Japanese Patent Laid-Open No. 2004-304771 discloses a technique that realizes pixel addition in a direction along a column. FIG. 16 is FIG. 2 of Japanese Patent Laid-Open No. 2004-304771, showing a signal processing unit corresponding to pixels of two columns. Here, reference numerals have been changed for ease of description. In FIG. 16, reference numerals 1200a to 1200c denote sampling capacitors, reference numeral 1570 denotes a horizontal signal line, reference numeral 1210 denotes a horizontal signal line capacitor, reference numeral 1600 denotes sample hold transistors, reference numeral 1610 denotes clamp capacitors, and reference numerals 1630a to 1630c denote sampling transistors. Reference numeral 1640 denotes clamp transistors, and reference numeral 1650 denotes column selection transistors. In FIG. 16, one column is provided with the three sampling capacitors 1200a to 1200c connected in parallel, which are independently selectable by the sampling transistors 1630a to 1630c. 
In Japanese Patent Laid-Open No. 2004-304771, when signals from pixels of three rows provided in the same column are to be added, the three sampling capacitors 1200a to 1200c are first made to hold signals of respective rows sequentially. Subsequently, the signals held in the sampling transistors 1630a to 1630c are added by turning on the sampling transistors 1630a to 1630c at the same time. Then, when the column selection transistor 1650 is turned on, the signal corresponding to the sum of the three rows is read via a horizontal signal line 1570. At this time a gain G1 by which a signal read via the horizontal signal line 1570 is to be multiplied is given by the following, letting Csp/3 be the capacitance value of the respective capacitors 1200a to 1200c, and Ccom be the capacitance value of the horizontal signal line capacitor 1210.G1=(Csp/3+Csp/3+Csp/3)/(Csp/3+Csp/3+Csp/3+Ccom)=Csp/(Csp+Ccom)  (1)
It is disclosed in Japanese Patent Laid-Open No. 2004-304771 that addition of two rows is performed in the case where four sampling capacitors are connected in parallel. As such a method, Japanese Patent Laid-Open No. 2004-304771 discloses a method in which a signal voltage of each row is stored in two sampling capacitors.
Thus, when two-row addition is to be performed, all the sampling capacitors can be utilized in the case where the sampling capacitors are provided in a number which is a multiple of two (four in the above example). However, the following case is not considered: the case where the sampling capacitors are provided in a number which is not a multiple of the number of rows to be added, specifically, when addition of two rows is to be performed in the case where three sampling capacitors are provided.